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1 ?2016 integrated device technology, inc. january 29, 2016 general description the 844003 is a three differential output lvds synthesizer designed to generate ethernet reference cloc k frequencies. using a 31.25mhz or 26.041666mhz, 18pf parallel resonant crystal, the following frequencies can be generated based on the settings of four frequency select pins (div_sel[a 1:a0], div_sel[b 1:b0]): 625mhz, 312.5mhz, 156.25mhz, and 125m hz. the 844003 has two output banks, bank a with one differential lvds output pair and ? bank b with two differential lvds output pairs. the two banks have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. the 844003 uses idt?s 3 rd generation low phase noise vco technology and can achieve 1ps or lower typical rms phase jitter, easily meeting ethernet jitter requirements. t he 844003 is packaged in a small 24-pin tssop package. features ? three lvds outputs on two banks, a bank with one lvds pair and b bank with two lvds output pairs ? using a 31.25mhz or 26.041666mhz crystal, the two output banks can be independently set for 625mhz, 312.5mhz, 156.25mhz or 125mhz ? selectable crystal oscillator interface or lvcmos/lvttl single-ended input ? vco range: 560mhz to 700mhz ? rms phase jitter @ 156.25mhz (1.875m hz - 20mhz): 0.63ps (typical) ? 3.3v output supply mode ? 0c to 70c ambient operating temperature ? available in lead-free (rohs 6) packaging block diagram 0 1 0 1 phase detector osc vco 0 = 20 (def ault) 1 = 24 0 0 1 0 1 2 (def ault) 1 0 4 1 1 5 0 0 1 0 1 2 1 0 4 (def ault) 1 1 5 fb_div oea pullup pu lldown:pullup pullup pu lldown pullup pu lldown pullup:pu lldown pu lldown pullup div_sela[1:0] vco_sel test_clk xtal_in xtal_out xtal_ sel fb_div div_selb[1:0] mr oeb qa0 nqa0 qb0 nqb0 qb1 nqb1 1 2 3 4 5 6 7 8 9 10 11 12 div_selb1 v ddo_b qb0 nqb0 qb1 nqb1 xtal_sel test_clk xtal_in xtal_out gnd div_sela1 div_selb0 vco_sel mr v ddo_a qa0 nqa0 oeb oea fb_div v dda v dd div_sela0 24 23 22 21 20 19 18 17 16 15 14 13 844003 24-lead tssop 4.40mm x 7.8mm x 0.92mm package body g package top view pin assignment 844003 datasheet femtoclock ? crystal-to-3.3v lvds ? frequency synthesizer
2 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet pin description and pin characteristic tables table 1. pin descriptions number name type description 1 div_selb0 input pulldown division select pin for bank b. lvcmos/lvttl interface levels. see table 3c. 2 vco_sel input pullup vco select pin. when low, the pll is bypassed and the crystal reference or test_clk (depending on xtal_sel setting) are passed directly to the output dividers. has an internal pullup resistor so the pll is not bypassed by default. lvcmos/lvttl interface levels. 3 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the true outputs qx to go low a nd the inverted outputs nqx to go high. when logic low, the internal divide rs and the outputs are enabled. has an internal pulldown resistor so the power-up default state of outputs and dividers are enabled. lvcmos/lvttl interface levels. 4v ddo_a power output supply pin for bank a outputs. 5 qa0 output differential output pair. lvds interface levels. 6 nqa0 output differential output pair. lvds interface levels. 7 oeb input pullup output enable bank b. active high out puts are enable. when logic high, the output pairs on bank b are enabled. when logic low, the output pairs are in a high impedance state. has an internal pullup resistor so the default power-up state of outputs are enabled . lvcmos/lvttl interface levels. see table 3f. 8 oea input pullup output enable bank a. active high output enable. when logic high, the output pair in bank a is enabled. when logic low, the output pair is in a high impedance state. has an internal pullup re sistor so the default power-up state of output is enabled. lvcmos/lvttl interface levels. see table 3e. 9 fb_div input pulldown feedback divide select. when low (default), the feedback divider is set for 20. when high, the feedback divider is set for 24. see table 3d lvcmos/lvttl interface levels. 10 v dda power analog supply pin. 11 v dd power core supply pin. 12 div_sela0 input pullup division select pin for bank a. lvcmos/lvttl interface levels. see table 3c. 13 div_sela1 input pulldown division select pin for bank a. lvcmos/lvttl interface levels. see table 3c. 14 gnd power power supply ground. 15 xtal_out output parallel resonant cryst al interface. xta l_out is the output. 16 xtal_in input parallel resonant crystal interface. xta l_in is the input. xt al_in is also the overdrive pin if you want to overdriv e the crystal circuit with a single-ended reference clock. 17 test_clk input pulldown single-ended reference clock input. has an internal pulldown resistor to pull to low state by default. can leave floating if using the crystal interface. lvcmos/lvttl interface levels. 18 xtal_sel input pullup crystal select pin. selects between t he single-ended test_clk or crystal interface. has an internal pullup resistor so the crystal inte rface is selected by default. lvcmos/lvttl interface levels. 1 9 nqb1 output differential output pair. lvds interface levels. 20 qb1 output differential output pair. lvds interface levels.
3 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics 21 nqb0 output differential output pair. lvds interface levels. 22 qb0 output differential output pair. lvds interface levels. 23 v ddo_b power output supply pin for bank b outputs. 24 div_selb1 input pullup division select pin for bank b. lvcmos/lvttl interface levels. see table 3c. symbol parameter test conditio ns minimum typical maximum units c in input capacitance lvcmos/ lvttl inputs 4pf r pulldown input pulldown resistor 51 k : r pullup input pullup resistor 51 k : number name type description
4 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet function tables table 3a. bank a frequency table 31.25 0 0 0 20 1 20 625 31.25 0 1 0 20 2 10 312.5 31.25 1 0 0 20 4 5 156.25 31.25 1 1 0 20 5 4 125 26.041666 0 0 1 24 1 24 625 26.041666 0 1 1 24 2 12 312.5 26.041666 1 0 1 24 4 6 156.25 26.041666 1 1 1 24 5 4.8 125 table 3b. bank b frequency table 31.25 0 0 0 20 1 20 625 31.25 0 1 0 20 2 10 312.5 31.25 1 0 0 20 4 5 156.25 31.25 1 1 0 20 5 4 125 26.041666 0 0 1 24 1 24 625 26.041666 0 1 1 24 2 12 312.5 26.041666 1 0 1 24 4 6 156.25 26.041666 1 1 1 24 5 4.8 125 inputs feedba ck divider bank a output divider m/n multiplicatio n factor qa0, nqa0 output frequency (mhz) crystal frequency (mhz) div_sela1 div_sela0 fb_div inputs feedback divider bank b output divider m/n multiplicatio n factor qb[1:0], nqb[1:0] output frequency (mhz) crystal frequency (mhz) div_selb1 div_selb0 fb_div
5 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet table 3c. output bank configuration select function table 0 0 1 0 0 1 0 1 2 0 1 2 1 0 4 1 0 4 1 1 5 1 1 5 table 3d. feedback divider configuration select function table 0 20 1 24 table 3e. oea select function table table 3f. oeb select function table 0 high-impedance high-impedance 0 high-impedance high-impedance 1 active active 1 active active inputs outputs inputs outputs div_sela1 div_sela0 qa div_selb1 div_selb0 qb inputs fb_div feedback divide inputs outputs inputs outputs oea qa0 nqa0 oeb qb[1:0] nqb[1:0]
6 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet absolute maximum ratings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current 10ma surge current 15ma package thermal impedance, t ja 78c/w (1m/s airflow) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. fu nctional operation of product at these conditions or any conditi ons beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. table 4a. power supply dc characteristics, v dd = v ddo_a = v ddo_b = 3.3v 5%, t a = 0c to 70c table 4b. lvcmos / lvttl dc characteristics, v dd = v ddo_a = v ddo_b = 3.3v 5%, t a = 0c to 70c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage 3.135 3.3 3.465 v v ddo_a, b output supply voltage 3.135 3.3 3.465 v i dd power supply current 99 ma i dda analog supply current 10 ma i ddo_a + i ddo_b output supply current 52 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current test_clk, mr, fb_div, div_sela1, div_selb0 v dd = v in = 3.465v 150 p a div_selb1, div_sela0, vco_sel, xtal_sel, oea, oeb v dd = v in = 3.465v 5 p a i il input low current test_clk, mr, fb_div, div_sela1, div_selb0 v dd = 3.465v, v in = 0v -5 p a div_selb1, div_sela0, vco_sel, xtal_sel, oea, oeb v dd = 3.465v, v in = 0v -150 p a
7 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet table 4c. lvds dc characteristics, v dd = v ddo_a = v ddo_b = 3.3v 5%, t a = 0c to 70c table 5. crystal characteristics note: validated using an 18pf parallel resonant crystal symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 350 mv ' v od v od magnitude change 0 50 mv v os offset voltage 1.4 v ' v os v os magnitude change 0 50 mv parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency fb_div = 20 28 35 mhz fb_div = 24 23.33 2 9 .16 mhz equivalent series resistance (esr) 50 : shunt capacitance 7pf drive level 1mw
8 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet ac electrical characteristics table 6. ac characteristics, v dd = v ddo_a = v ddo_b = 3.3v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow grea ter than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: defined as skew within a bank of output s at the same voltages and with equal load conditions. note 2: defined as skew between outputs at the same supply voltages and with equal load conditions. measured at the output differential crosspoints. note 3: please refer to the phase noise plot. note 4: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditio ns minimum typical maximum units f out output frequency range output divider = 1 560 700 mhz output divider = 2 280 350 mhz output divider = 4 140 175 mhz output divider = 5 112 140 mhz t sk (b) bank skew, note 1 3ps t sk (o) output skew, note 2, 4 outputs @ same frequency 15 ps outputs @ different frequencies 30 ps tjit(?) rms phase jitter (random); note 3 625mhz (1.875mhz - 20mhz) 0.55 ps 312.5mhz (1.875mhz - 20mhz) 0.5 9 ps 156.25mhz (1.875mhz - 20mhz) 0.63 ps 125mhz (1.875mhz - 20mhz) 0.64 ps t r / t f output rise/fall time 20% to 80% 325 ps odc output duty cycle 50 %
9 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet typical phase noise at 156.25mhz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 noise power (dbc/hz) 100 1k 10k 100k offset frequency (hz) 1m 10m 100m 10gb ethernet filter raw phase noise data phase noise result by adding 10gb ethernet filter to raw data 156.25mhz, rms phase jitter (random), 1.875mhz to 20mhz = 0.63ps
10 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet applications information recommendations for unused input and output pins i nputs: crystal input: for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k : resistor can be tied from xtal_in to ground. test_clk input: for applications not requiring the use of the test clock, it can be left floating. though not required, but for additional protection, a 1k : resistor can be tied from the test_clk to ground. lvcmos control pins: all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k : resistor can be used. outputs: lv d s all unused lvds output pairs can be either left floating or terminated with 100 : across. if they are left float ing, we recommend that there is no trace attached.
11 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 1a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this c onfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 : applications, r1 and r2 can be 100 : . this can also be accomplished by removing r1 and changing r2 to 50 : . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 1b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl terminati on with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 1a. general diagram for lvcmos driver to xtal input interface figure 1b. general diagram for lvpec l driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
12 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet lvds driver termination for a general lvds interface, the recommended value for the termi - nation impedance (z t ) is between 9 0 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmis - sion-line environment. in order to avoid any transmission-line reflec - tion issues, the components should be surface mounted and must be pla ced as close to the receiver as possible. idt offers a full line of lvds compliant devices with two type s of output structures: current source and voltage source. the standard termination schematic as shown in figure 2a can be used with either type of output structure. figure 2b , which can also be used with both output types, is an op - tional termination with center tap c apaci tance to help filter common mode noise. the capacitor value should be approximately 50pf. if us - ing a non-standard termination, it is recommend ed to contact idt and confirm if the output structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be veri - fied for compatibility with the output. lv d s ? driver lv d s ? driver lv d s ? receiver lv d s ? receiver z t c z o ? z t z o ? z t z t 2 z t 2 figure 2a. standard termination figure 2b. optional termination lvds termination
13 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet schematic layout figure 3 shows an example 844003 application schematic. the sche - matic example focuses on functional connections and is not configu - ration specific with the exception of the selection of the 31.25mhz crystal frequency. this decision requires that fb_div = 0. if a 26.041666mhz crystal had been selected, then fb_div = 1. refer to the pin description and functional ta bles in the datasheet to ensure the logic control inputs are properly set. input and out put terminations shown are intended as examples only and may not represent the ex - act user configuration. in this example an 18pf parallel resonant 31.25mhz crystal is used with load caps c4 = c5 = 22pf. the load caps shown were used to tune the idt device characterization board and are recommended for frequency accuracy, but these may be adjusted for different board layouts. crystals with different load capacities may be used, but the load capacitors will have to be changed accordingly. if different crys - tal types are used, please consult idt for recommendations. the schematic example shows two different lvds output termina - tions; the standard termination 100 : shunt termination for an lvds compliant receiver and an ac coupled termination for a non- lvds dif - ferential receiver. the ac coupled termination requires that the de - signer select the values of r4 and r5 in order to center the lvds swing within the common mode range of the receiver. in addition the designer must make sure that the target receiver will operate reliably with the lvds swing, which is reduc ed relative to other logic families such as hcsl or lvpecl. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is requ ired. the 844003 provides separate v dd, v dda, v ddo_a and v ddo_b pins to isolate any high speed switching noise at the outputs from coupling into the internal pll. in order to achieve the best possible filtering, it is highly recommend - ed that the 0.1f capacitors be placed on the 844003 side of the pcb as close to the power pins as possible. this is represented by the placement of these capacitors in th e schematic. if space is limited, the ferrite beads, 10uf capacitor s and the 0.1uf capacitors connect - ed directly to 3.3v can be placed on the opposite side of the pcb. if space permits, place all filter co mponents on the device side of the board. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for a wide range of noise frequencies. this low-pass filter st arts to attenuate noise at approximately 10khz. if a specific frequency noise compone nt is known, such as switching power supplies frequencies, it is recommended that component val - ues be adjusted and if required, additional filtering be added. addi - tionally, good general design practices for power plane voltage stability suggests adding bulk capac itance in the local area of all de - vices.
vco_sel xtal _ s e l di v_ s e l b0 di v_ s e l a0 di v_ s e l a1 di v_ s e l b1 c10 0.1uf vdd vdd_rx receiver + - alternate ac coupled lvds termination (select r4 and r5 t o center the lvds swing in the common mode center of the recei ver. ) zo = 50 ohm zo = 50 ohm r2 50 r3 50 c3 0.01uf c1 0.1u c2 0.1u r4 r5 nqb1 qb1 c11 10uf c21 0. 1uf fb2 bl m 1 8b b 2 2 1 sn 1 1 2 place each 0.1uf bypass cap directly ad ja cen t to t he co rr es po nd ing v dd o_ x pi n. c7 0.1uf 3.3v c8 10uf fb1 blm18bb221sn1 1 2 r6 10 c9 10uf to logic input pins c12 0. 1uf vd d to l o gi c in pu t pi ns vdd ru 2 not install ru1 1k rd 2 1k rd1 not install set logic input to '1' set logic input to '0' logic cont rol input examples c16 0. 1uf place each 0.1uf bypass cap directly adj ac en t to it s re sp ec ti ve vd d or vdd a pi n. c13 0. 1uf 3.3v lvds ter minati on lvds r eceiver + - zo = 50 ohm nqa0 zo = 50 ohm r1 100 qa0 vdda qb0 nqb0 c4 22pf c5 22pf x1 31. 25 mh z (18pf ) 3. 3 v r7 43 fb_div zo = 50 ohm ro =7 ohm lvcmos_driv er u1 div_selb0 1 div_selb1 24 vco_sel 2 mr 3 fb_div 9 div_sela0 12 div_sela1 13 xtal_ou t 15 xtal_in 16 test_clk 17 xtal_sel 18 qa 0 5 nqa0 6 oeb 7 oea 8 nqb1 19 qb 1 20 nqb0 21 qb 0 22 vddo_a 4 vdda 10 vd d 11 vddo_b 23 gnd 14 mr oe b oe a 14 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet figure 3. 844003 application schematic
15 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet power considerations this section provides information on power dissi pation and junction temperature for the 844003. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 844003 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. to t a l po w e r _max = v dd_max * (i dd_max + i dda_max + i ddo_max ) = 3.465v * 1 99 ma = 689.5mw 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature is 125c. the equation for tj is as follows: tj = t ja * pd_total + t a tj = junction temperature t ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the app ropriate junction-to-ambient thermal resistance t ja must be used. assuming 1m/s air flow and a multi-layer board, the appropriate value is 78c/w per table 7 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.6 9 0w * 78c/w = 123.8c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary d epending on the number of loaded outputs, supply voltage, air flow , and the type of board (multi-layer). table 7. thermal resistance t ja for 24-lead tssop package t ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 82.3c/w 78.0c/w 75. 9 c/w
16 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet reliability information table 8. t ja vs. air flow table for a 24-lead tssop transistor count the transistor count for 844003 is: 33 9 4 package outline and dimensions package outline - g suffix for 24 lead tssop table 9. package dimensions reference document: jedec publication 9 5, mo-153 t ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 82.3c/w 78.0c/w 75. 9 c/w all dimensions in millimeters symbol minimum maimum n 24 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.1 9 0.30 c 0.0 9 0.20 d 7.70 7. 9 0 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 d 0 8 aaa 0.10
17 ?2016 integrated device technology, inc. january 29, 2016 844003 datasheet ordering information table 10. ordering information part/order number marking package shipping packaging temperature 844003aglf ics844003aglf 24 lead tssop, lead-free tube 0c to 70c 844003aglft ics844003aglf 24 lead tssop, lead-free tape & reel 0c to 70c
disclaimer integrated device technology, inc. (idt) and its subs idiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any li cense under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this produ ct is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices o r critical medical instruments. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2016 integrated device technology, inc. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

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